高中化学教育、高中化学奥赛

Serdes;Deserializer;Phase-locked Loop (pll);Serializer;Serial Link;Transceiver;Linear Regulator;Phase Interpolator;Dual Loop

1. Clock-data recovery circuit for serial link communication system, has sampler to receive data signal having variable data bit-rate in response to clock signal.
KIM D; WEI J; FRANS Y; BYSTROM T; NGUYEN N; DONNELLY K
公开日期: 2007-07-26 申请日期: 2004-09-28 公开号: JP2007520913A

2. Clock-data recovery circuit for serial link communication system, has sampler to receive data signal having variable data bit-rate in response to clock signal.
RAMBUS INC
KIM D; WEI J; FRANS Y; BYSTROM T; NGUYEN N; DONNELLY K
公开日期: 2006-06-08 申请日期: 2004-09-28 公开号: DE202004020988U1

技术咨询